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<section-title-en>2.4 Address Spaces</section-title-en>
<section-title-ch>2.4 地址空间</section-title-ch>
<p-en>
	Software written for the Intel architecture accesses the computer's resources using four distinct physical address spaces, shown in Figure 9. The address spaces overlap partially, in both purpose and contents, which can lead to confusion. This section gives a high-level overview of the physical address spaces defined by the Intel architecture, with an emphasis on their purpose and the methods used to manage them.
</p-en>
<p-ch>
	为Intel架构编写的软件使用四个不同的物理地址空间访问计算机的资源，如图9所示。这些地址空间在目的和内容上都有部分重叠，这可能导致混淆。本节对英特尔架构定义的物理地址空间进行了高层次的概述，重点介绍了它们的目的和管理它们的方法。
</p-ch>
<img src="fig.9.jpg" />
<p-en>Figure 9: The four physical address spaces used by an Intel CPU. The registers and MSRs are internal to the CPU, while the memory and I/O address spaces are used to communicate with DRAM and other devices via system buses.</p-en>
<p-ch>图9：Intel CPU使用的四个物理地址空间。寄存器和MSR是CPU内部的，而内存和I/O地址空间则用于通过系统总线与DRAM和其他设备通信。</p-ch>
<p-en>
	The register space consists of names that are used to access the CPU's register file, which is the only memory that operates at the CPU's clock frequency and can be used without any latency penalty. The register space is defined by the CPU's architecture, and documented in the SDM.
</p-en>
<p-ch>
	寄存器空间由用于访问CPU的寄存器文件的名称组成，它是唯一以CPU的时钟频率运行的存储器，可以在没有任何延迟惩罚的情况下使用。寄存器空间由CPU的架构定义，并在SDM中记录。
</p-ch>
<p-en>
	Some registers, such as the Control Registers (CRs) play specific roles in configuring the CPU's operation. For example, CR3 plays a central role in address translation (§2.5). These registers can only be accessed by system software. The rest of the registers make up an application's execution context (§2.6), which is essentially a high-speed scratch space. These registers can be accessed at all privilege levels, and their allocation is managed by the software's compiler. Many CPU instructions only operate on data in registers, and only place their results in registers.
</p-en>
<p-ch>
	有些寄存器，如控制寄存器（CR）在配置CPU的操作中起着特定的作用。例如，CR3在地址转换中起着核心作用（§2.5）。这些寄存器只能由系统软件访问。其余的寄存器构成了应用程序的执行上下文(§2.6)，它本质上是一个高速涂写空间。这些寄存器可以被所有权限级别的人访问，它们的分配由软件的编译器管理。许多CPU指令只对寄存器中的数据进行操作，并且只将其结果放在寄存器中。
</p-ch>
<p-en>
	The memory space, generally referred to as the address space, or the physical address space, consists of 2^36 (64 GB) – 2^40 (1 TB) addresses. The memory space is primarily used to access DRAM, but it is also used to communicate with memory-mapped devices that read memory requests off a system bus and write replies for the CPU. Some CPU instructions can read their inputs from the memory space, or store the results using the memory space.
</p-en>
<p-ch>
	内存空间，一般称为地址空间，或物理地址空间，由2^36（64GB）-2^40（1TB）地址组成。内存空间主要用于访问DRAM，但也用于与内存映射设备通信，从系统总线上读取内存请求，并为CPU写入回复。一些CPU指令可以从内存空间读取它们的输入，或者使用内存空间存储结果。
</p-ch>
<p-en>
	A better-known example of memory mapping is that at computer startup, memory addresses 0xFFFF0000 - 0xFFFFFFFF (the 64 KB of memory right below the 4 GB mark) are mapped to a flash memory device that holds the first stage of the code that bootstraps the computer.
</p-en>
<p-ch>
	一个比较著名的内存映射的例子是，在计算机启动时，内存地址0xFFFF0000-0xFFFFFFFF（4GB标志正下方的64KB内存）被映射到一个闪存设备上，这个闪存设备保存着启动计算机的代码的第一阶段。
</p-ch>
<p-en>
	The memory space is partitioned between devices and DRAM by the computer's firmware during the bootstrapping process. Sometimes, system software includes motherboard-specific code that modifies the memory space partitioning. The OS kernel relies on address translation, described in §2.5, to control the applications' access to the memory space. The hypervisor relies on the same mechanism to control the guest OSs.
</p-en>
<p-ch>
	在启动过程中，计算机的固件会将内存空间在设备和DRAM之间进行分区。有时，系统软件包括主板专用代码，其修改内存空间分区。操作系统内核依靠§2.5中描述的地址转换来控制应用程序对内存空间的访问。管理程序依靠同样的机制来控制客体操作系统。
</p-ch>
<p-en>
	The input/output (I/O) space consists of 2^16 I/O addresses, usually called ports. The I/O ports are used exclusively to communicate with devices. The CPU provides specific instructions for reading from and writing to the I/O space. I/O ports are allocated to devices by formal or de-facto standards. For example, ports 0xCF8 and 0xCFC are always used to access the PCI express (§2.9.1) configuration space.
</p-en>
<p-ch>
	输入/输出（I/O）空间由2^16个I/O地址组成，通常称为端口。I/O端口专门用于与设备通信。CPU提供了从I/O空间读取和写入的特定指令。I/O端口是通过正式或事实标准分配给设备的。例如，端口0xCF8和0xCFC总是用来访问PCI express（§2.9.1）配置空间。
</p-ch>
<p-en>
	The CPU implements a mechanism for system software to provide fine-grained I/O access to applications. However, all modern kernels restrict application software from accessing the I/O space directly, in order to limit the damage potential of application bugs.
</p-en>
<p-ch>
	CPU实现了系统软件为应用软件提供细粒度的I/O访问的机制。然而，所有现代内核都限制应用软件直接访问I/O空间，以限制应用软件错误的破坏可能性。
</p-ch>
<p-en>
	The Model-Specific Register (MSR) space consists of 2^32 MSRs, which are used to configure the CPU's operation. The MSR space was initially intended for the use of CPU model-specific firmware, but some MSRs have been promoted to architectural MSR status, making their semantics a part of the Intel architecture. For example, architectural MSR 0x10 holds a high-resolution monotonically increasing time-stamp counter.
</p-en>
<p-ch>
	模型特定寄存器（MSR）空间由2^32个MSR组成，用于配置CPU的操作。MSR空间最初的目的是供CPU模型特定固件使用，但一些MSR已经晋升为架构MSR状态，使其语义成为英特尔架构的一部分。例如，架构MSR 0x10持有一个高分辨率单调递增的时间戳计数器。
</p-ch>
<p-en>
	The CPU provides instructions for reading from and writing to the MSR space. The instructions can only be used by system software. Some MSRs are also exposed by instructions accessible to applications. For example, applications can read the time-stamp counter via the RDTSC and RDTSCP instructions, which are very useful for benchmarking and optimizing software.
</p-en>
<p-ch>
	CPU提供了从MSR空间读写的指令。这些指令只能由系统软件使用。一些MSR也被应用程序可访问的指令所暴露。例如，应用程序可以通过RDTSC和RDTSCP指令读取时间戳计数器，这对基准测试和优化软件非常有用。
</p-ch>

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